The present invention relates generally to semiconductor device processing techniques and, more particularly, to a method of forming narrow fins for fin-shaped field effect transistor (finFET) devices using asymmetrically spaced mandrels.
The escalating demands for high density and performance associated with ultra large scale integrated (ULSI) circuit devices have required certain design features, such as shrinking gate lengths, high reliability and increased manufacturing throughput. The continued reduction of design features has challenged the limitations of conventional fabrication techniques.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects (e.g., excessive leakage between the source and drain regions) become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent one type of structure that has been considered as a candidate for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A finFET is a recent double-gate structure that exhibits good short channel behavior, and includes a channel formed in a vertical fin. The finFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
In particular, a conventional spacer image transfer (SIT) process is typically used to form a dense array of fins. In order to fabricate multiple fin devices, either a contact bar process or an epitaxy process is needed to merge the initially formed multiple fins. However, the former approach leads to extra parasitic capacitance, while the latter approach results in process complexity (e.g., spacer removal on fin sidewalls). In addition, epitaxial fin merging also constraints the fin spacing (e.g., equal spacing is needed between the pair of fins formed on a single mandrel and between those formed on neighboring mandrels, and different epitaxial deposition time is needed if fin thickness is changed), and leads to extra parasitic capacitance and resistance due to epitaxial semiconductor growth on top of the fins. Furthermore, a hardmask is also needed to avoid epitaxial growth on top of the gate structure.